This invention relates to insulated gate field effect transistor (IGFET) logic circuits and more particularly to logic circuits which use capacitively coupled voltage feedback (bootstrapping) in their load transistor.
IGFET circuits using capacitively coupled voltage feedback from the source electrode to the gate electrode of the load transistor (bootstrap circuits) are known in the art and are commonly found in both p-channel metal-oxide-semiconductor (PMOS) and n-channel metal-oxide-semiconductor (NMOS) integrated circuits. In accordance with the bootstrap technique, a typical application of which is the prior art circuit shown in FIG. 1, the output voltage of the circuit is coupled from the output terminal to the gate of the load transistor through a capacitance which is initially charged to some voltage by a charging circuit. The bootstrap technique provides a circuit whose output can rise to substantially the full power supply (VDD power supply) voltage and one with increased output drive capability and switching speed. In addition, the bootstrap technique eliminates the need for an additional off-chip power supply otherwise necessary to bias the gate of the load transistor at a voltage sufficient to keep the load transistor in the "triode region" of its operating characteristics. Eliminating the off-chip bias supply, which must provide sizeable currents to charge the gate capacitance of the load transistor, significantly reduces the power dissipation of the circuit.
An example of a prior art circuit using the bootstrap technique as shown in FIG. 1 is described in U.S. Pat. No. 3,506,851 by R. W. Polkinghorn et al. One problem with prior art bootstrap circuits such as the one described in the Polkinghorn patent is that the output voltage cannot be maintained at VDD for long periods of time. When such a circuit is held in the "high" logic state, junction leakage currents in the transistors which are coupled to the feedback capacitance drains away the charge stored in the capacitance and causes the output voltage to shift from VDD to VDD-2 VT (VT is the threshold voltage of the transistors) in typically several milliseconds. The shifting output voltage of a bootstrap circuit may produce erroneous switching in load circuits which are driven by the output voltage, and therefore imposes greater noise immunity requirements on such load circuits.
A prior art solution to alleviate the shifting output voltage problem in bootstrap circuits is disclosed in U.S. Pat. No. 3,649,843 by D. J. Redwine et al. The Redwine patent describes a bootstrap circuit (as shown in FIG. 2) similar to the one described in the Polkinghorn patent but with the addition of a sustaining transistor connected between the output terminal and the VDD supply terminal. However, the Redwine circuit is deficient in that its steady-state output voltage for the "high" logic state is clamped to only VDD-VT rather than to VDD as is desirable. Therefore, the above-mentioned noise immunity problem is still present when low values of VDD are used. Moreover, the addition of the sustaining transistor also increases the capacitive loading on the output node and thereby decreases the switching speed of the circuit.
In many applications it is desirable from the standpoint of reducing power dissipation to use a technique called power gating whereby the load transistor of a circuit is switched to its nonconducting state ("off" state) while the circuit is in its "low" logic state. Power gating eliminates a dc current path from the VDD power supply through the load and driver transistors to ground and thus reduces the power dissipation of the circuit. Although prior art bootstrap circuits may be power gated, the above-mentioned problem of shifting output voltage limits their usefulness in such applications.
Therefore, it is clear that a need exists for an improved bootstrap circuit which would permit its output voltage to be maintained at full VDD supply voltage for indefinite periods, and also for one which can be power gated.
Accordingly, it is an object of the present invention to provide an improved bootstrap circuit in which the steady-state output voltage for the "high" logic state is maintained at substantially full power supply voltage.
It is another object of the present invention to provide an improved bootstrap circuit which can be power gated.
It is a further object of the present invention to provide an improved bootstrap circuit having low power dissipation and high switching speed.